Alekseyev Michael Projects Description icon

Alekseyev Michael Projects Description



НазваниеAlekseyev Michael Projects Description
Дата конвертации21.07.2012
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Alekseyev Michael Projects Description


Project 4,5,6, 7, 8

Company: StRC "Elvees", Moscow

Job: RISC+DSP+ Peripherals cores in one chip (SoC Designing)

Duration: 3.5 years and go on

General Job Description:

RISC+DSP cores on one chip. OMAP technology chip. Synthesis digital circuit from Verilog description. Simulate design at logic and netlist level using SDF-file. Verilog behavioral and projects restructuring for best synthesis result. Synthesis DSP core at 0.8 , 0.5, 0.25 micron. Serial port, Link port and UART synthesis and writing testing schedule for them. Synthesis whole chip (SOC) at 0.8, 0.5, 0.25, 0.18 micron. System On Chip Designing: Simulation, Synthesis, STA, Layout, Physical Synthesis

success chip:

MC_12S 0.25micron technology, 4million transistors, 100Mhz (25mm2 square)

MC_23S 0.25micron technology, 4million transistors, 120Mhz (25mm2 square)

MC_12 0.25micron technology, 18million transistors, 120Mhz (100mm2 square)

MC_24 0.25micron technology, 18million transistors, 120Mhz (100mm2 square)

MC_0128 0.18micron technology, 6million transistors, 300Mhz (25mm2 square)

Picture MC_24 chip in package: http://alekseevm.chat.ru/MC_24_N1.jpg

Evaluation Board for MC_12 is shipped for order: http://www.elvees.ru/news/1892_mc12.shtml


Operating Systems: Unix, Windows 9x, XP, Linux

Environment: Simulation, Synthesis, Layout creation

Size of the team: 10

Role in the team: Leading Engineer

Project 3


Company: JSC "Angstrem", Moscow

Job: Code converter Design

Duration: 2 months

General Job Description:

1592XM4-001(~1000 EG). Design for parallel to sequential code converter. Military application project. Prelayout and Postlayout simulation using SDF-file. Frequency 60 MHz. Select testing strategy for design circuit.

Tested wafer and microschemes on HP 82000 tester.


^ Operating Systems: Unix, Windows9x

Environment: OrCAD, Cadence

Size of the team: 3

Role in the team: Front-end Design Engineer

Project 2

Company: JSC "Angstrem", Moscow

Job: DSP Design

Duration: 5 months

General Job Description:

1592XM1-001(~50000 EG).
Design for processing of a real-time signal. Military application project. Prelayout and Postlayout simulation using SDF-file. Frequency 13 MHz.Tested wafer and microschemes on HP 82000 tester.


^ Operating Systems: Unix, Windows9x

Environment: OrCAD, Cadence

Size of the team: 4

Role in the team: Front-end Design Engineer

Project 1

Company: JSC "Angstrem", Moscow

Job: ASIC Library Design

Duration: 2 years

General Job Description:

Created circuit of cells (for core and pads) at a transistor level. Designed topology of cells.

Characterization of cell for what was created system of Automatic Cell Characterization (ACC system). This program written on SKILL (Cadence environment language). Results are TLF-file for library of core and pad cell.

ACC system used Spice for characterization.

Development of behavioral models of cells on Verilog, and on VHDL (using Vital).

Developed a testing design powering up all cell

Compiled testbench for this test design. Test design permit to certify all core and pad cells. Select testing strategy for 1592XM ASIC gate array.

Created macroblock for ASIC: Ram, Rom, Multiplier, FIFO.These macroblock go through all characterization and tested steps as all ASIC primitives.Tested wafer and microschemes on HP 82000 tester.


Operating Systems: Unix

Languages: SKILL

Size of the team: 5

Role in the team: ASIC Design Engineer

Alekseyev Michael Projects descriptions September 25 2005 г.




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