Address: Moscow, Russia icon

Address: Moscow, Russia

НазваниеAddress: Moscow, Russia
Дата конвертации23.08.2012
Размер14.61 Kb.

Michael N. Alekseyev

OBJECTIVE: Challenging VLSI ASIC Designer position.

Address: Moscow, Russia.


Phone: +7 903 7391684

Homepage: /Welcome to my homepage/

Date of birth: September 30, 1976

Languages: Russian, spoken English.

Employment history and professional experience
Oct 2005 – Sept 2006 : DongbuAnam Semiconductor (former name) < > Project Manager.

  • Library Design Kit: Testing and setting up the flow. Design Library characterization chip. Functional, timing and IR-drop effect measurement for 130nm:
    RTL design, Simulation, Synthesis (Design Compiler Synopsys), STA and P&R management in Cadence environment

  • Library high-precision characterization chip (10ps accuracy) 130nm:
    Synthesis, STA and P&R managements in Synopsys Environment (DC and Astro)

  • SOC chip – 130nm, CPU, 2 DSP cores, USB 1.1, UART, Video (IN OUT), ADC, DAC
    CPU and main System - 170Mhz; DSP – 270Mhz
    Synthesis, STA and P&R managements. Communications between Chip-design-team (out of Korea) and foundry-service group in DongbuAnam. New 130nm technology attestation project. Status – successful, chip fully operates.

  • Setting up Cadence Design Flow based on SOC project:
    Std cell Library, IO, SRAM, RF library debug in Simulation, Synthesis and P&R stages, RTL Compiler (NEW) testing

May 2001 – Oct 2005 : Company "Elvees" <> Leading Engineer.

  • RISC+DSP cores in one chip. OMAP technology chip. System On Chip designing technology

  • Synthesis digital circuit from Verilog description. Simulate design at logic and netlist level using SDF-file from topology.

  • Verilog behavioral and projects restructuring for best synthesis result.

  • Serial port, Link port and UART synthesis and creating testing schedule.

  • Static Timing Analysis of all chip

  • Creating Layout for all chip except Power and Verification stage. Clock tree and reset tree designing. Physical Synthesis

  • Synthesis whole chip (SOC) at 0.8, 0.5, 0.25, 0.18 micron

  • Have 6 successfully projects: MC_12S, MC_23S (see Project form page:

October 1998 – May 2001: Company "Angstrem" <> CAD Engineer.

  • Development of the system of Automatic Cell Characterization (ACC) for ASIC Library.

  • ASIC Library Design (core and pads)
    [channelles gate array 1592XMx - 100000 EG; 1.2 micron technology]

  • Participated in creation of topology of cells of a core and pads. Perform LVS (layout versus schematic).

  • Development of the test circuits permitting to certify the created library of cells and macroblocks. Building of complicated testbenches using VHDL/Verilog for the design. Select test strategy.

  • Development of the design flow in the OrCAD environment (with further translation of the circuit on the platform Cadence using EDIF). Technical documentation at all design flow stages.

  • Prelayout and Postlayout simulation of the circuit, using SDF-file in Express (OrCAD) and Verilog-XL (Cadence).

  • Shared in testing of wafers and microcircuit on HP82000 tester.

  • Have 2 successfully projects: 1592XM1-001 (~50000 EG) and 1592XM4-001 (~1000 EG). Both are for military application.


  • 8 years of experience in HDL languages as VHDL(using Vital) / Verilog.

  • Opus DB & SKILL (Cadence) programming – 1.5 year.

  • ASIC library design.

  • Synthesis digital design from VHDL/Verilog description in Synopsys (DA,DC,LC,PT), Leonardo Spectrum, Build Gates.

  • Development digital circuit in OrCAD (Capture, Express, Spice) – 3 years.

  • Development ASIC digital circuit in Cadence – 7 years.

  • Prelayout and Postlayout simulation of the circuit, using SDF-file in Verilog-XL / NC-Sim (Cadence) and Express (OrCAD).

  • CAD systems: Synopsys (Design Analyzer, Library Compiler, Prime Time), Cadence (Virtuoso; Verilog-XL, NC-Verilog, Pearl; Analog Artist; Synergy, Spice, SOC Encounter, LDV); OrCAD.

  • SOC designing, building ClockTree in CTS, LVS (layout versus schematic), Full chip STA, SOC Encounter scripting

  • Compilation testbench for digital design.

  • Development FPGA digital circuit in Altera MAX-plus II.

  • 3 years Assembly Z80, MCS51 programming.

  • Programming language: UNIX Shell Script (sh, ksh), Pascal, BASIC.

  • OS: Windows 9X/NT/2000,XP, Unix (Solaris), Linux;


1993-1998: Master Degree of Electrical Engineering of Ural State Technical University (c. Ekaterinburg). <>

Radio engineering faculty, specialty "Electrical Engineering".

Main dissertation topic: "Development of a microprocessor control device for a washing machine "Vyatka an automaton". Developed the circuit of a microprocessor control device and written a time schedule control for a washing machine on an assembly MCS51.

Additional information

I’m easy to study, is efficient and is executive. I have good communication skill and like work in team.

Michael Alekseyev CV October 19, 2006


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